Sykatia : Delivering Excellence

Careers

Sykatiya Technologies Private Ltd is an exciting Design Services venture formed by like-minded people. Our focus lies in delivering quality solutions to our customers. The Company's Core Value emphasizes the commitment to our employees and customers.

We are seeking highly motivated individuals with strong technical skills. Individuals who are looking to advance their career and help the company grow can apply.

Currently all our positions are based in Bangalore, India

Current requirements include activities involving :

Digital/mixed-signal optimal DFT architecture definition rationalizing across test time/cost, coverage, dppm and customer quality
Plan DFT activities for self and the team
DFT logic integration and verification
Achieve coverage metrics
DFT automation and methodology
Gate Level DFT verification
Pattern generation, verification and delivery
Post silicon bring-up and production support

Looking for suitable hands-on engineers with 8+ years of experience in SOC/IP/Sub-System DFT.

Responsible and accountable with pro-active communication skills and a proven track record with the following:

Be a strong technical contributor who can work in a team environment
Be able and willing to provide technical mentorship to team members.
Should be able to work across cultural/functional/geographic boundaries
Need to be experienced in of all the aspects relating to

Scan/ATPG
Scan synthesis, coverage metrics by fault-models – stuck-at, delay & Bridging,
Memory BIST
Test Mode STA
Test power estimation, Boundary Scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing
Expert in EDA tools

Must have strong debug skills and automation savvy.
Post-Silicon debug and support

Apply Now by filling the below form.

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Looking for suitable engineers with 3+ years of experience in Digital, Mixed-Signal SOC/IP/Sub-System DFT.

Should have sound understanding of all the Design for Test requirements

Should be able to comprehend DFT architecture, architecture limitations, schedule, volume of the task(s).
Be aware of all the aspects relating to

Scan/ATPG
Scan synthesis, coverage metrics by fault-models – stuck-at, delay & Bridging,
Memory bist
Test power estimation, Bounday scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing,
Post-Silicon debug and support

Have good knowledge of test STA
Need good debug skills and be automation savvy
Have good understanding of Gate-Level simulations and its nuancest
Be able to translate tool generated patterns to ATE platform
Be able to help in silicon debug both on ATE and at system level
Have experience in industry standard EDA ATPG and Simulation tools

Apply Now by filling the below form.

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Note : If you find any difficulty in uploading resume in above form, Plz forward the resume directly to careers@sykatiya.com

Current requirements include activities involving :

Definition of Verification scope, goals, strategy, methodology, flows
Project planning, resource allocation, schedule tracking, driving team to meet project deadlines
Build Verification environment - test-bench, BFMs, traffic generators, checkers and models
Verification flow setup - SW build, RTL/gate level/low power simulation, regression and Silicon production support flows
Constrained random verification and assertion based verification
Write and debug test-cases. Achieve functional and code coverage closure
Gate level, low power implementation verification
Prototyping and support: FPGA, HW acceleration, Emulation
Functional test pattern generation, verification and delivery. Post silicon bring-up and production support

Looking for suitable hands-on engineers with 8+ years of experience in SOC/IP/Sub-System DV.

Be a good technical leader who can assimilate customer requirements and help device execution plans
Be responsible and accountable with pro-active communication skills and a proven track record
Should be able to work across cultural/functional/geographic boundariesStrong technical contributor
Should be able to work across cultural/functional/geographic boundaries
Strong domain knowledge on one or more protocols such as PCIe, USB, Ethernet, ARM, AHB/AXI, AMBA, OCP, MIPI
Be proficient in one or more HVLs (SystemVerilog, Specman, VERA)
Have hands-on expertise in building complex verification environments and setting up verification flows
Should have worked on SOC verification with constrained random methodology (eRM/VMM/OVM/UVM) on one or more projects
Have expertise with Verification EDA tools. Strong debug skills and Automation savvy
Be experienced in all aspects related to

Writing and debugging testcases
Functional and Code coverage techniques, analysis and closure
Gate-Level simulations and its nuances
Post-Silicon debug and support

Apply Now by filling the below form.

Name *

Email *

Phone *

Exp *

DOB *

Gender *

Male Female

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Note : If you find any difficulty in uploading resume in above form, Plz forward the resume directly to careers@sykatiya.com

Looking for suitable engineers with 3+ years of experience in SOC/IP/Sub-System Design Verification.

Be a strong technical contributor who can work in a team environment
Should have sound understanding of all the design verification requirements
Should be able to comprehend Design architecture, architecture limitations, schedule, volume of the task(s).
Good knowledge in Verilog and / or VHDL is a must
Proficiency in one or more HVLs (SystemVerilog, Specman, VERA)
Should have worked on SOC verification with constrained random methodology (eRM/VMM/OVM/UVM) on one or more projects
Good knowledge of one or more Verification EDA tools
Methodical approach to debug and Automation savvy with experience in any one or more of the scripting language (Perl, Tcl, Python etc..)
Should be aware of all aspects related to

Writing and debugging testcases
Functional and Code coverage techniques, analysis and closure
Gate-Level simulations and its nuances
Post-Silicon debug and support

Apply Now by filling the below form.

Name *

Email *

Phone *

Exp *

DOB *

Gender *

Male Female

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Note : If you find any difficulty in uploading resume in above form, Plz forward the resume directly to careers@sykatiya.com

Current requirements include activities involving :

Physical design implementation of multimillion gate SoC designs in latest CMOS process technologies such as 45nm, 28nm, 20nm
Synthesis, full chip floor plan, power grid design, IO ring design, clock tree design, place and route of full chip and critical blocks
IR drop analysis, cross talk analysis, power analysis, timing optimization/closure and physical verification
Methodology development/enhancement, Vendor tool evaluation/benchmarking and integration
Plan PD activities for self and the team
Post-Silicon debug and support on PD related issues on need basis

Looking for suitable hands-on engineers with 8+ years of experience in implementation and tape out of multimillion gate designs.

Be a good technical leader who can assimilate customer requirements and help device execution plans
Be responsible and accountable with pro-active communication skills and a proven track record
Should be able to work across cultural/functional/geographic boundaries
Be experienced in all aspects related to

Synthesis, full chip floor plan, power grid design, IO ring design, clock tree design, clock tree synthesis, place and route of full chip and critical blocks
IR drop analysis, cross talk analysis, power analysis, timing optimization/closure, physical verification
Post-Silicon debug and support on PD related issues on need basis

Have hands-on experience or familiarity in one or more of the following areas would be an added advantage
Be involved in complete chip design activities - from RTL to GDSII on multiple SoCs
Low power design implementation
Need expertise with one or more industry standard Physical Design EDA tools
Need expertise with of any one or more of the scripting language like Perl, Tcl, Python, Unix Make/Shell Scripts, awk, sed etc

Apply Now by filling the below form.

Name *

Email *

Phone *

Exp *

DOB *

Gender *

Male Female

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Note : If you find any difficulty in uploading resume in above form, Plz forward the resume directly to careers@sykatiya.com

Looking for suitable engineers with 3+ years of experience in physical design implementation of multimillion gate SoCs.

Be a strong individual contributor who can work in a team environment
Should have sound understanding of all the physical design implementation requirements
Have good knowledge of one or more Industry standard physical design EDA tools
Should be aware of all aspects related to

Synthesis, full chip floor plan, power grid design, IO ring design, clock tree design, clock tree synthesis, place and route of full chip and critical blocks
IR drop analysis, cross talk analysis, power analysis, timing optimization/closure, physical verification

Have hands-on experience or familiarity in one or more of the following areas would be an added advantage

Involvement in complete chip design activities - from RTL to GDSII on multiple SoCs
Experience with CPU, DSP, Wireless and Automotive related IPs
Low power design implementation
Methodology development, vendor tool evaluation/benchmarking and integration
Be able to help in silicon debug on physical design implementation issues on need basis

Apply Now by filling the below form.

Name *

Email *

Phone *

Exp *

DOB *

Gender *

Male Female

Upload your Resume *

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Note : If you find any difficulty in uploading resume in above form, Plz forward the resume directly to careers@sykatiya.com